Increasing the density of integrated circuit devices generally requires reduction of the size of the transistors used in the devices in order to incorporate more transistors into the integrated circuit. To reduce the size of the transistors, it is generally desirable to reduce the area of the active regions in the integrated circuit. In addition, it generally is desirable to reduce the area of the device isolation regions used to separate the active regions of the integrated circuit.
One technique for forming device isolation regions involves the local oxidation of silicon (LOCOS). According to this technique, an insulating oxide layer is grown between active regions by thermally oxidizing silicon substrate regions between the active regions. However, as the oxidation process tends to extend laterally across the face of the substrate as well as vertically into the regions, so-called "bird's beaks" may be produced at the edges of the active regions which may encroach on and undesirably narrow the active regions. In addition, the heat treatment used for oxidation may induce defects in the substrate silicon through heat stress and thermal diffusion of ion-implanted impurities.
An alternative to LOCOS techniques are trench isolation methods wherein a trench is formed in a semiconductor substrate and filled with an insulating material such as silicon dioxide. Although trench isolation can provide effective isolation between devices, the profile of the side walls of the trench may effect the stability of the devices. As illustrated in FIGS. 1A-1B, a transistor isolated by a trench having a sharp upper edge as in FIG. 1A may exhibit the undesirable drain current vs. gate voltage characteristic shown in FIG. 1B. A concentration of the electric field near the sharp edge of the trench may cause a "hump" as illustrated in FIG. 1B. The hump may lead to undesirable operating characteristics, e.g., a stepped gate voltage turn-on characteristic for some source to drain voltage levels. In FIG. 2A, a trench having rounded upper edges is illustrated, with FIG. 2B illustrating improved drain current vs. gate voltage characteristics produced by the rounded-edge trench.
A conventional technique for forming a rounded-edge trench is described in U.S. Pat. No. 4,857,477 to Kanamori. As illustrated in FIGS. 3A-3C, this technique includes sequentially forming an oxide layer and a first mask layer on a substrate 10 and patterning the first mask layer and the oxide layer to expose a portion of the substrate 10 between masking regions 14. Spacers 16 are then formed by forming a second masking layer on the substrate and anisotropically etching the second masking layer to leave the spacers 16 disposed adjacent the masking regions 14. The substrate 10 is then etched using the spacers 16 and the mask layer 14 as a mask to form a trench 18. The spacers 16 are then removed, and the exposed substrate portions etched, typically using a rapid dry-etching technique, to form rounded edges A.
Although this technique effectively produces a rounded-edge trench, the processes involved are generally complicated, typically requiring multiple photomasking and etching steps. The large number of steps may undesirably increase the time and expense required to manufacture the integrated circuit.